What Is TRI Data Type in Verilog?


Larry Thompson

The TRI data type in Verilog is a specialized type that represents tri-state logic. Tri-state logic is a common feature in digital circuit design where a signal can have three states: high (1), low (0), or high impedance (Z). The high impedance state allows multiple devices to share the same wire without interfering with each other.

Understanding Tri-State Logic

Tri-state logic is often used in bus systems, where multiple devices need to send and receive data over the same set of wires. Each device can either drive the bus with a value of 0 or 1, or it can release the bus and put it into a high impedance state.

In other words, when a signal is in the high impedance state, it acts as if it’s disconnected from the circuit. This allows other devices to drive the bus without causing any conflicts or short circuits.

The TRI Data Type

In Verilog, the TRI data type is used to represent tri-state signals. It’s declared using the keyword `tri`, followed by the size specifier (optional) and variable name. Here’s an example:

tri [7:0] data_bus;

This declares a 8-bit tri-state signal named `data_bus`. The size specifier `[7:0]` indicates that `data_bus` is an 8-bit signal, where bit 7 represents the most significant bit and bit 0 represents the least significant bit.

Assigning Values to TRI Signals

To assign a value to a tri-state signal, you can use an assignment statement just like any other variable in Verilog. However, there are some rules that need to be followed:

  • Driving: To drive a value of 1 or 0 onto a tri-state signal, you can use a regular assignment statement. For example:
    data_bus = 8'b10101010;
  • Releasing: To release a tri-state signal and put it into a high impedance state, you can use the `z` or `Z` value. For example:
    data_bus = Z;
  • Pulling: You can also pull a tri-state signal to a specific value using the `x` or `X` value. This is useful when you want to simulate an open circuit condition. For example:
    data_bus = X;

Using TRI Signals in Modules

In Verilog, tri-state signals are often used in module interfaces to provide a common bus for communication between different modules. When designing modules that use tri-state signals, it’s important to consider the timing and potential conflicts that may arise.

To ensure proper operation of a bus system, it’s necessary to coordinate the driving and releasing of tri-state signals among all devices connected to the bus. This coordination is typically achieved using control signals or protocols specific to the application.


The TRI data type in Verilog is an essential tool for designing digital circuits with tri-state logic. By allowing signals to be in a high impedance state, tri-state logic enables multiple devices to share the same wire without causing conflicts or short circuits.

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